Tft-lcd array substrate and manufacturing method thereof

ABSTRACT

A thin film transistor liquid crystal display (TFT-LCD) array substrate comprises a gate line, a data line, a pixel electrode and a thin film transistor. The pixel electrode and the thin film transistor are formed in a pixel region defined by intersecting of the gate line and the data line, and the thin film transistor comprises a gate electrode, a semiconductor layer, a source electrode and a drain electrode. Two separate parts of the surface of the semiconductor layer are treated by a surface treatment to form into an ohmic contact layer, and the source electrode and the drain electrode are connected with the semiconductor layer through the ohmic contact layer in the two separate parts, respectively.

BACKGROUND

Embodiments of the present invention relate to a thin film transistorliquid crystal display (TFT-LCD) array substrate and a method ofmanufacturing the same.

Thin film transistor liquid crystal displays (TFT-LCDs) device have theadvantages of small volume, low energy consumption, low radiation andthe like, and thus have prevailed in the flat plate display market. Asfor TFT-LCDs, the performance, yield and cost are mainly determined byan array substrate of a TFT-LCD and a manufacturing method thereof. Inorder to effectively reduce the cost and improve the yield, the processof manufacturing a TFT-LCD array substrate is gradually simplified fromthe initial 7-mask process to the present 4-mask process employing ahalf-tone mask or a gray-tone mask.

Presently, the manufacture of a TFT-LCD array substrate can be performedby forming a series of thin film patterns through a series of patterningprocess. Generally, one layer of thin film pattern is formed through onepatterning process. In the 4-mask process, an active layer, a date line,a source electrode, a drain electrode and a TFT channel region can beformed by one patterning process with a half-tone mask or a gray-tonemask. The active layer comprises a semiconductor film and a dopedsemiconductor film (ohmic contact film) that are stacked in order.During forming the TFT channel region, the doped semiconductor film isetched by a dry etching process. In order to etch away the dopedsemiconductor film in the TFT channel region and realize the uniformityand selectivity of such etch, an over-etching process is performed untila portion of the semiconductor film provided below the dopedsemiconductor film is etched. Thus, the semiconductor film must have alarge thickness, such as 1500 Å-3000 Å.

According to the definition of the turn-off current of a thin filmtransistor, the turn-off current of the thin film transistor isproportional to the thickness of the semiconductor film. The turn-offcurrent of the thin film transistor is increased with the increase ofthe thickness of the semiconductor film. Because of the increasedturn-off current of the thin film transistor, the leakage current isincreased, the period, during which the voltage of a pixel electrode isheld, is shortened, and thus the performance of the TFT-LCD arraysubstrate comprising the thin film transistor as a switch element for apixel is degraded. Furthermore, during etching the doped semiconductorfilm and the semiconductor film through a conventional dry etchingprocess, the surface of the semiconductor film in the TFT channel regionis roughed due to the physical bombing, and thus the performance of theTFT-LCD array substrate is further degraded. In addition, during formingthe TFT channel region by using the half-tone mask or the gray-tonemask, failures (for example, the short circuit between the sourceelectrode and the drain electrode, the open circuit of the channelregion, and the like) are caused by the multiple-step etching process,and thus the yield is severely reduced.

SUMMARY

According to an embodiment of the invention, a thin film transistorliquid crystal display (TFT-LCD) array substrate comprising a gate line,a data line, a pixel electrode and a thin film transistor, wherein thepixel electrode and the thin film transistor are formed in a pixelregion defined by intersecting of the gate line and the data line, andthe thin film transistor comprises a gate electrode, a semiconductorlayer, a source electrode and a drain electrode, and wherein twoseparate parts of the surface of the semiconductor layer are treated bya surface treatment to form into an ohmic contact layer, and the sourceelectrode and the drain electrode are connected with the semiconductorlayer through the ohmic contact layer in the two separate parts,respectively.

According to another embodiment of the invention, a method ofmanufacturing a thin film transistor liquid crystal display (TFT-LCD)array substrate comprising: Step 1 of sequentially depositing atransparent conductive film and a gate metal film on a substrate, andpatterning the transparent conductive film and the gate metal film toform a pixel electrode, a gate line and a gate electrode; Step 2 ofdepositing a gate insulating layer and a semiconductor film on thesubstrate after the Step 1 and patterning the semiconductor film to forma semiconductor layer, wherein two separate parts of the surface of thesemiconductor layer is treated by a surface treatment process to forminto an ohmic contact layer; and Step 3 of depositing a source/drainmetal film on the substrate after the Step 2, and patterning thesource/drain metal film to form a data line, a source electrode and adrain electrode by a patterning process, wherein the source electrodeand the drain electrode respectively are connected with thesemiconductor layer through the ohmic contact layer in the two separateparts.

Further scope of applicability of the present invention will becomeapparent from the detailed description given hereinafter. However, itshould be understood that the detailed description and specificexamples, while indicating preferred embodiments of the invention, aregiven by way of illustration only, since various changes andmodifications within the spirit and scope of the invention will becomeapparent to those skilled in the art from the following detaileddescription.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from thedetailed description given hereinafter and the accompanying drawingswhich are given by way of illustration only, and thus are not limitativeof the present invention and wherein:

FIG. 1 is a plan view showing a first embodiment of a TFT-LCD arraysubstrate according to the invention;

FIG. 2 is a sectional view taken along line A1-A1 in FIG. 1;

FIG. 3 is a plan view after a first patterning process of the firstembodiment of the TFT-LCD array substrate according to the invention;

FIG. 4 is a sectional view taken along the line A2-A2 in FIG. 3;

FIG. 5 is a sectional view taken along the line A2-A2 after exposing anddeveloping a photoresist layer in the first patterning process of thefirst embodiment of the TFT-LCD array substrate according to theinvention;

FIG. 6 is a sectional view taken along the line A2-A2 after a firstetching process in the first patterning process of the first embodimentof the TFT-LCD array substrate according to the invention;

FIG. 7 is a sectional view taken along the line A2-A2 after an ashingprocess in the first patterning process of the first embodiment of theTFT-LCD array substrate according to the invention;

FIG. 8 is a sectional view taken along the line A2-A2 after a secondetching process in the first patterning process of the first embodimentof the TFT-LCD array substrate according to the invention;

FIG. 9 is a plan view after a second patterning process of the firstembodiment of the TFT-LCD array substrate according to the invention;

FIG. 10 is a sectional view taken along line A3-A3 in FIG. 9;

FIG. 11 is a plan view after a third patterning process of the firstembodiment of the TFT-LCD array substrate according to the invention;

FIG. 12 is a sectional view taken along line A4-A4 in FIG. 11;

FIG. 13 is a plan view showing a second embodiment of a TFT-LCD arraysubstrate according to the invention;

FIG. 14 is a sectional view taken along line B1-B1 in FIG. 1;

FIG. 15 is a plan view after a second patterning process of the secondembodiment of the TFT-LCD array substrate according to the invention;

FIG. 16 is a sectional view taken along line B3-B3 in FIG. 15;

FIG. 17 is a sectional view taken along the line B3-B3 after exposingand developing a photoresist layer in the second patterning process ofthe second embodiment of the TFT-LCD array substrate according to theinvention;

FIG. 18 is a sectional view taken along the line B3-B3 after a firstetching process in the second patterning process of the secondembodiment of the TFT-LCD array substrate according to the invention;

FIG. 19 is a sectional view taken along the line B3-B3 after a firstashing process in the second patterning process of the second embodimentof the TFT-LCD array substrate according to the invention;

FIG. 20 is a sectional view taken along the line B3-B3 after a secondetching process in the second patterning process of the secondembodiment of the TFT-LCD array substrate according to the invention;

FIG. 21 is a sectional view taken along the line B3-B3 after a secondashing process in the second patterning process of the second embodimentof the TFT-LCD array substrate according to the invention;

FIG. 22 is a sectional view taken along the line B3-B3 after a thirdetching process in the second patterning process of the secondembodiment of the TFT-LCD array substrate according to the invention;and

FIG. 23 is a sectional view taken along the line B3-B3 after a surfacetreatment process in the second patterning process of the secondembodiment of the TFT-LCD array substrate according to the invention.

DESCRIPTION OF THE EMBODIMENTS

Hereinafter, the embodiments of the invention will be described indetail with the accompanying drawings.

FIG. 1 is a plan view showing a first embodiment of a TFT-LCD arraysubstrate according to the invention, and FIG. 2 is a sectional viewtaken along line A1-A1 in FIG. 1.

As shown in FIG. 1 and FIG. 2, the TFT-LCD array substrate according tothis embodiment comprises gate lines 10, data lines 11, common electrodelines 12, pixel electrodes 9 and thin film transistors. A pixel regionis defined by intersecting of one gate line 10 and one data line 11perpendicular to each other. One thin film transistor and one pixelelectrode are formed in each pixel region. The gate line 10 is used tosupply the turn-on (“ON”) signals to the thin film transistor, the dataline 11 is used to supply the data signals to the pixel electrode 9, andthe common electrode line 12 is used to constitute storage capacitorwith the pixel electrode 9.

Specifically, the TFT-LCD array substrate according to this embodimentcomprises a gate electrode 2, the gate line 10 and the pixel electrode9, which are all formed on a substrate 1. The gate electrode 2 isconnected with the gate line 10. The pixel electrode 9 is formed on thesubstrate 1 and within the pixel region. A gate insulating layer 3 isformed on the gate electrode 2, the gate line 10 and the pixel electrode9 to cover the entirety of the substrate 1. A semiconductor layer 4 isformed on the gate insulating layer 3 and positioned over the gateelectrode 2. A passivation layer 8 is formed on the semiconductor layer4 to cover the entirety of the substrate 1. A first via hole 8 a, asecond via hole 8 b and a third via hole 8 c are provided in thepassivation layer 8. The first via hole 8 a is provided on the pixelelectrode 9 and exposes a portion of the surface of the pixel electrode9. The second via hole 8 b and the third via hole 8 c are provided onthe semiconductor layer 4 and each expose a portion of the surface ofthe semiconductor layer 4. The surface of the semiconductor layer 4exposed by the second via hole 8 b and the third via hole 8 c comprisesan ohmic contact layer 4 a formed by surface treatment as describedbelow. The data line 11, the common electrode line 12, the sourceelectrode 6 and the drain electrode 7 are formed on the passivationlayer 8. One end of the source electrode 6 is connected with the dataline 11, the other end thereof is positioned over the semiconductorlayer 4 and connected with the semiconductor layer 4 through the ohmiccontact layer 4 a in the third via hole 8 c. One end of the drainelectrode 7 is connected with the pixel electrode 9 through the firstvia hole 8 a, the other end thereof is positioned over the semiconductorlayer 4 and connected with the semiconductor layer 4 through the ohmiccontact layer 4 a in the second via hole 8 b. A TFT channel region isformed between the source electrode 6 and the drain electrode 7. Inanother embodiment, the common electrode line 12 is not formed.

In this embodiment, the thickness of the semiconductor layer 4 is about500-1500 Å, and preferably is about 500-1000 Å. The surface treatment tothe semiconductor layer 4 is a phosphorizing treatment using PH₃ gas, inwhich the RF power is about 5-12 KW, the atmospheric pressure is about100-400 mT and the flow rate is about 1000-4000 sccm. In addition, thegate electrode 2, the gate line 10 and the pixel electrode 9 may beformed in a single patterning process or in different patterningprocesses.

FIG. 3 to FIG. 12 are schematic views showing the manufacture process ofthe first embodiment of the TFT-LCD array substrate according to theinvention. Hereinafter, the described patterning process may comprisethe processes of applying photoresist, masking, exposing and developingof photoresist, etching, removing remaining photoresist, and the like.For example, a positive photoresist is used as an example in apatterning process.

FIG. 3 is a plan view after a first patterning process of the firstembodiment of the TFT-LCD array substrate according to the invention,and FIG. 4 is a sectional view taken along the line A2-A2 in FIG. 3.

A transparent conductive film with a thickness of about 300-600 Å and agate metal film with a thickness of about 500-4000 Å are deposited onthe substrate 1 by a magnetron sputtering method, a thermal evaporationmethod or other film formation method. The transparent conductive filmmay be formed by indium tin oxide (ITO), indium zinc oxide (IZO),aluminum zinc oxide (AZO) and the like or by other metal or metal oxide.The gate metal film may be formed by a metal such as Cr, W, Ti, Ta, Mo,Al, Cu and the like or an alloy of the above metals. In addition, thegate metal film may have a multi-layer structure formed by anycombination of the above metals. By a patterning process using ahalf-tone mask or a gray-tone mask, the gate electrode 2, the gate line10 and the pixel electrode 9 are formed on the substrate, as shown inFIG. 3 and FIG. 4. Such patterning process is described in detail asfollows.

FIG. 5 is a sectional view taken along the line A2-A2 after exposing anddeveloping a photoresist layer in the first patterning process of thefirst embodiment of the TFT-LCD array substrate according to theinvention.

After the transparent conductive film 21 and the gate metal film 22 aresequentially deposited on the substrate 1, a photoresist layer 30 isapplied on the gate metal film 22. The photoresist layer 30 is exposedby using a half-tone mask or a gray tone mask to form a completelyexposed region A, an unexposed region B and a partially exposed regionC. The unexposed region B corresponds to the regions of the gate lineand the gate electrode, the partially exposed region C corresponds tothe region of the pixel electrode, and the completely exposed region Acorresponds to the region other than the above regions. After thedeveloping process is performed, the thickness of the photoresist in theunexposed region B is not substantially changed to form aphotoresist-completely-retained region, the photoresist in thecompletely exposed region A is completely removed to form aphotoresist-completely-removed region, and the thickness of thephotoresist in the partially exposed region C is decreased to form aphotoresist-partially-retained region, as shown in FIG. 5.

FIG. 6 is a sectional view taken along the line A2-A2 after a firstetching process in the first patterning process of the first embodimentof the TFT-LCD array substrate according to the invention. By the firstetching process, the gate metal film 22 and the transparent conductivefilm 21 in the completely exposed region A are etched away so that thegate line 10 and the gate electrode 2 are formed, as shown in FIG. 6.

FIG. 7 is a sectional view taken along the line A2-A2 after an achingprocess in the first patterning process of the first embodiment of theTFT-LCD array substrate according to the invention. By the ashingprocess, the thickness of the photoresist layer 30 is decreased so thatthe photoresist in the partially exposed region C is completely removedto expose the gate metal film 22 in this region, as shown in FIG. 7.Since the thickness of photoresist in the unexposed region B is biggerthan that in the partially exposed region C, the unexposed region B isstill covered by remaining photoresist with a certain thickness afterthe ashing process.

FIG. 8 is a sectional view taken along the line A2-A2 after a secondetching process in the first patterning process of the first embodimentof the TFT-LCD array substrate according to the invention. By the secondpatterning process, the gate metal film in the partially exposed regionC is etched so that in this region the gate metal film is etched awayand the transparent conductive film is exposed, and thus the exposedtransparent conductive film in this region forms the pixel electrode 9,as shown in FIG. 8.

Then, the remaining photoresist is removed to complete the firstpatterning process of the TFT-LCD array substrate in this embodiment. Asshown in FIG. 3 and FIG. 4, the pixel electrode is formed on thesubstrate 1 and the transparent conductive film is retained below thegate line 10 and the gate electrode 2 after the first patterningprocess.

FIG. 9 is a plan view after a second patterning process of the firstembodiment of the TFT-LCD array substrate according to the invention,and FIG. 10 is a sectional view taken along line A3-A3 in FIG. 9.

On the substrate 1 with the pattern shown in FIG. 3, the gate insulatinglayer 3 with a thickness of about 3000-5000 Å and a semiconductor filmwith a thickness of about 500-1500 Å are sequentially deposited by aplasma enhanced chemical vapor deposition (PECVD) method or other filmformation method. The gate insulating layer 3 may be formed of an oxide,a nitride or an oxynitride, and the corresponding source gas thereof maybe a mixture of SiH₄, NH₃ and N₂ or a mixture of SiH₂Cl₂, NH₃ and N₂.The semiconductor film may be an amorphous silicon film, and thecorresponding source gases thereof may be a mixture of SiH₄ and H₂ or amixture of SiH₂Cl₂ and H₂. Then, the semiconductor layer 4 is formed bya patterning process using a normal mask, as shown in FIG. 9 and FIG.10. After the second patterning process, the gate insulating layer 3 isformed on the gate electrode 2, the gate line 10 and the pixel electrode9 to cover the entirety of the substrate 1, and the semiconductor layer4 is formed on the gate insulating layer 3 and positioned over the gateelectrode 2.

FIG. 11 is a plan view after a third patterning process of the firstembodiment of the TFT-LCD array substrate according to the invention,and FIG. 12 is a sectional view taken along line A4-A4 in FIG. 11.

On the substrate with the pattern shown in FIG. 9, the passivation layer8 with a thickness of about 700-2000 Å is deposited by a PECVD method orother film formation method. The passivation layer 8 may be formed by anoxide, a nitride or an oxynitride, and the corresponding source gasthereof may be a mixture of SiH₄, NH₃ and N₂ or a mixture of SiH₂Cl₂,NH₃ and N₂. The first via hole 8 a, the second via hole 8 b and thethird via hole 8 c are formed by a patterning process using a normalmask. The first via hole 8 a is provided on the pixel electrode 9 andnear the gate electrode 2. The passivation layer 8 and the gateinsulating layer 3 in the first via hole 8 a are etched away to exposethe surface of the pixel electrode 9 in the first via hole 8 a. Thesecond via hole 8 b and the third via hole 8 c are provided on thesemiconductor layer 4. The passivation layer 8 in both the second viahole 8 b and the third via hole 8 c are etched away to exposed thesurface of the semiconductor layer in the second via hole 8 b and thethird via hole 8 c. The surface of the semiconductor layer 4 exposed inthe second via hole 8 b and the third via hole 8 c is treated with asurface treatment process so that the surface of the semiconductor layer4 in the second via hole 8 b and the third via hole 8 c is formed intothe ohmic contact layer 4 a, as shown in FIG. 11 and FIG. 12. In thethird patterning process, the gate pad via hole (not shown) may besimultaneously formed in the gate pad region. The structure of the gatepad via hole are well-known to those skilled in the art and detaileddescriptions thereof are omitted here for simplicity. The surfacetreatment in this embodiment is a phosphorizing treatment using PH₃ gas,in which the RF power is about 5-12 KW, the atmospheric pressure isabout 100-400 mT and the flow rate is about 1000-4000 seem. The secondvia hole 8 b and the third via hole 8 c may be provided on both sides ofthe semiconductor layer 4 over the gate electrode 2 (as shown thisembodiment), or on both sides of the semiconductor layer 4 outside ofthe gate electrode 2. The shape of the via holes may be rectangular,elliptical or circular, and the length, width and other geometricalparameters thereof may be determined depending on the practicalrequirements.

Finally, a source/drain metal film with a thickness of about 2000-3000 Åis deposited on the substrate with the pattern shown in FIG. 12 by usinga magnetron sputtering method, a thermal evaporation method or otherfilm formation method. The source/drain metal film may be formed by ametal such as Cr, W, Ti, Ta, Mo, Al, Cu and the like or an alloy of theabove metals. In addition, the source/drain metal film may have amulti-layer structure formed by any combination of the above metals. Thedata line 11, the common electrode line 12, the source electrode 6 andthe drain electrode 7 are formed by a patterning process using a normalmask, as shown in FIG. 1 and FIG. 2. After this patterning process, oneend of the source electrode 6 is connected with the data line 11, theother end thereof is positioned over the semiconductor layer 4 andconnected with the semiconductor layer 4 through the ohmic contact layer4 a in the third via hole 8 c. One end of the drain electrode 7 isconnected with the pixel electrode 9 through the first via hole 8 a, theother end thereof is positioned over the semiconductor layer 4 andconnected with the semiconductor layer 4 through the ohmic contact layer4 a in the second via hole 8 b. The TFT channel region is formed betweenthe source electrode 6 and the drain electrode 7. The common electrodeline 12 is formed in the pixel region and constitutes the storagecapacitor with the pixel electrode 9.

According to this embodiment of the TFT-LCD array substrate, the pixelelectrode, the gate line and the gate electrode are formed by the firstpatterning process; the semiconductor layer is formed by the secondpatterning process; the first via hole, the second via hole and thethird via hole are formed by the third patterning process, and thesurface of the semiconductor layer exposed in the second via hole andthe third via hole is treated by a surface treatment process so that thesurface of the semiconductor layer in the second via hole and the thirdvia hole is formed into the ohmic contact layer; the data line, thecommon electrode line, the source electrode and the drain electrode areformed by the fourth patterning process. Compared with the TFT-LCD arraysubstrate manufactured with the conventional 4-mask process using ahalf-tone mask or a gray-tone mask, the TFT-LCD array substrate in thisembodiment has the following advantages.

1. In this embodiment, the TFT channel region is formed by a patterningprocess using a normal mask after the semiconductor layer is formed, andthe semiconductor layer is not over-etched, unlike the conventionalprocess. Thus, the semiconductor layer in this embodiment can have asmall thickness of about 500-1500 Å, preferably about 500-1000 Å. Thethickness of the semiconductor layer is decreased, the turn-off currentof the thin film transistor can be significantly reduced, the period ofholding the voltage of the pixel electrode can be increased and theperformance of the TFT-LCD array substrate can be improved. In addition,the thickness of the semiconductor layer is decreased, the contactresistance can be reduced and the carrier mobility in the TFT channelregion can be improved.

2. In this embodiment, the semiconductor layer is kept from beingphysically bombed during the TFT channel region is formed, and thus thesurface of the semiconductor layer is not damaged and the performance ofthe TFT-LCD array substrate can be further improved.

3. In this embodiment, the failures generated during the TFT channelregion is formed by the conventional multiple-step etching process witha half-tone mask or a gray-tone mask can be avoided by forming the TFTchannel region through a patterning process with a normal mask, and thusthe product yield can be improved.

4. In this embodiment, the surface of the semiconductor layer in thesecond via hole and the third via hole is treated and formed into theohmic contact layer. In this way, not only the electrical connectionbetween the semiconductor layer and the source/drain electrode can beensured, but also deposition of the conventional doped semiconductorlayer can be omitted. That is, the process of depositing the dopedsemiconductor layer is omitted. Thus, the manufacture cost can bereduced, the process period can be shortened and the productionefficiency can be improved.

FIG. 13 is a plan view showing a second embodiment of a TFT-LCD arraysubstrate according to the invention, and FIG. 14 is a sectional viewtaken along line B1-B1 in FIG. 1. As shown in FIG. 13 and FIG. 14, theTFT-LCD array substrate in this embodiment is manufactured by adifferent production process, in which the structures of the gate line10, the data line 11, the common electrode line 12, the pixel electrode9 and the like are similar to those in the first embodiment except forthe structure of the thin film transistor.

Specifically, the TFT-LCD array substrate according to this embodimentcomprises the gate electrode 2, the gate line 10 and the pixel electrode9, which are all formed on a substrate 1. The gate electrode 2 isconnected with the gate line 10. The pixel electrode 9 is formed on thesubstrate 1 and within the pixel region. The gate insulating layer 3 isformed on the gate electrode 2, the gate line 10 and the pixel electrode9 to cover the entirety of the substrate 1. The first via hole 8 a isprovided in the gate insulating layer 3 and positioned on the pixelelectrode 9. The semiconductor layer 4 is formed on the gate insulatinglayer 3 and over the gate electrode 2. A blocking layer 5 is provided onthe semiconductor layer 4, and the surface of the semiconductor layer 4on both sides of the blocking layer 5 is treated with a surfacetreatment process to form into the ohmic contact layer 4 a. One end ofthe source electrode 6 is connected with the data line 11, and the otherend thereof is positioned on the ohmic contact layer 4 a on one side ofthe blocking layer 5 and connected with the semiconductor layer 4through the ohmic contact layer 4 a. One end of the drain electrode 7 isconnected with the pixel electrode 9 through the first via hole 8 a, andthe other end thereof is positioned on the ohmic contact layer 4 a onthe other side of the blocking layer 5 and connected with thesemiconductor layer 4 through the ohmic contact layer 4 a. The TFTchannel region is formed between the source electrode 6 and the drainelectrode 7, and the blocking layer 5 is formed to cover the TFT channelregion.

FIG. 15 to FIG. 23 are schematic views showing the manufacture processof the second embodiment of the TFT-LCD array substrate according to theinvention.

The first patterning process and the structural patterns formed in thisembodiment (such as the pixel electrode, the gate line and the gateelectrode) are similar to those shown in FIG. 3 and FIG. 4 of the firstembodiment, so the detailed descriptions thereof are omitted here forsimplicity.

FIG. 15 is a plan view after a second patterning process of the secondembodiment of the TFT-LCD array substrate according to the invention,and FIG. 16 is a sectional view taken along line B3-B3 in FIG. 15.

On the substrate with the patterns of the pixel electrode, the gate lineand the gate electrode, the gate insulating layer 3 with a thickness ofabout 3000-5000 Å, the semiconductor film with a thickness of about500-1500 Å and a blocking film with a thickness of about 1000-3000 Å aresequentially deposited by a PECVD method or other film formation method.The gate insulating layer and the blocking film may be formed by anoxide, nitride or oxynitride, and the corresponding source gases thereofmay be a mixture of SiH₄, NH₃ and N₂ or a mixture of SiH₂Cl₂, NH₃ andN₂. The semiconductor film may be an amorphous silicon film, and thecorresponding source gases thereof may be a mixture of SiH₄ and H₂ or amixture of SiH₂Cl₂ and H₂. The semiconductor layer 4, the blocking layer5 and the first via hole 8 a are formed by a patterning process with atriple-tone mask, and then the surface of the semiconductor layer 4 onboth sides of the blocking layer 5 is treated by a surface treatmentprocess and therefore formed into the ohmic contact layer, as shown inFIG. 15 and FIG. 16. The semiconductor layer 4 is formed on the gateinsulating layer 3 and over the gate electrode 2. The blocking layer 5is formed on the semiconductor layer 4 and exposes the semiconductorlayer 4 on both sides thereof. The first via hole 8 a is provided at thepixel electrode 9 and near the gate electrode 2. In this patterningprocess, the gate pad via hole (not shown) can be simultaneously formedin the gate pad region. The structure of the gate pad via hole arewell-known to those skilled in the art and the detailed descriptionsthereof are omitted here. This patterning process will be described indetail as follows.

FIG. 17 is a sectional view taken along the line B3-B3 after exposingand developing a phororesist layer in the second patterning process ofthe second embodiment of the TFT-LCD array substrate according to theinvention. Firstly, the gate insulating layer 3, the semiconductor film23 and the blocking film 24 are sequentially deposited by a PECVD methodor other film formation method. Then, a photoresist layer 30 is appliedon the blocking film 24. The photoresist layer 30 is exposed by using atriple-tone mask to form a completely exposed region A, an unexposedregion B, a first partially exposed region C and a second partiallyexposed region D. The completely exposed region A corresponds to theregion of the first via hole, the unexposed region B corresponds to theregion of the blocking layer, the second partially exposed region Dcorresponds to the region of the semiconductor layer, and the firstpartially exposed region C corresponds to the region other than theabove regions. After the developing process is performed, the thicknessof the photoresist in the unexposed region B is not substantiallychanged to form a photoresist-completely-retained region. Thephotoresist in the completely exposed region A is completely removed toform a photoresist-completely-removed region. The thickness of thephotoresist in both of the first partially exposed region C and thesecond partially exposed region D is decreased to form a firstphotoresist-partially-retained region and a secondphotoresist-partially-retained region. The thickness of the photoresistin the second photoresist-partially-retained region is larger than thatin the first photoresist-partially-retained region but smaller than thatin the photoresist-completely-retained region, as shown in FIG. 17. Theemployed triple-tone mask has three regions with differenttransmissivities and an opaque region, and thus four regions withdifferent exposure levels can be obtained by using the triple-tone mask.Various forms of tripe-tone mask, such as a half-tone mask with a slit,can be used in this patterning process.

FIG. 18 is a sectional view taken along the line B3-B3 after a firstetching process in the second patterning process of the secondembodiment of the TFT-LCD array substrate according to the invention. Bythe first etching process, the blocking film 24, the semiconductor film23 and the gate insulating layer 3 in the completely exposed region A isetched away to form the first via hole 8 a. The first via hole 8 a isprovided on the pixel electrode 9 and near the gate electrode 2. Theblocking film 24, the semiconductor film 23 and the gate insulatinglayer 3 in the first via hole 8 a are etched away to expose the pixelelectrode 9 in first via hole 8 a, as shown in FIG. 18. In thispatterning process, the gate pad via hole can be simultaneously formedin the gate pad region.

FIG. 19 is a sectional view taken along the line B3-B3 after a firstashing process in the second patterning process of the second embodimentof the TFT-LCD array substrate according to the invention. By the firstashing process, the photoresist layer 30 in the first partially exposedregion C is completely removed to expose the blocking film 24 in thisregion, as shown in FIG. 19. Since the thickness of the photoresist inthe unexposed region B and the second partially exposed region D islarger than that in the first partially exposed region C, the unexposedregion B and the second partially exposed region D are still covered bythe remaining photoresist after this ashing process, and the thicknessof the photoresist in the unexposed region B is still larger than thatin the second partially exposed region D.

FIG. 20 is a sectional view taken along the line B3-B3 after a secondetching process in the second patterning process of the secondembodiment of the TFT-LCD array substrate according to the invention. Bythe second etching process, the blocking film 24 and the semiconductorfilm 23 in the first partially exposed region C are etched away to formthe semiconductor layer 4. The semiconductor layer 4 is formed on thegate insulating layer 3 and positioned over the gate electrode 2, asshown in FIG. 20.

FIG. 21 is a sectional view taken along the line B3-B3 after a secondashing process in the second patterning process of the second embodimentof the TFT-LCD array substrate according to the invention. By the secondashing process, the photoresist layer 30 in the second partially exposedregion D is completely removed to expose the blocking film 24 in thisregion, as shown in FIG. 21. Since the thickness of the photoresist inthe unexposed region B is larger than that in the second partiallyexposed region D, the unexposed region B is still covered by theremaining photoresist with a certain thickness after this process.

FIG. 22 is a sectional view taken along the line B3-B3 after a thirdetching process in the second patterning process of the secondembodiment of the TFT-LCD array substrate according to the invention. Bythe third etching process, the blocking film 24 in the second partiallyexposed region D is etched away to form the blocking layer 5. As shownin FIG. 22, the blocking layer 5 is formed on semiconductor layer 4, andthe semiconductor layer 4 is exposed on both sides of the blocking layer5.

FIG. 23 is a sectional view taken along the line B3-B3 after a surfacetreatment process in the second patterning process of the secondembodiment of the TFT-LCD array substrate according to the invention. Bythe surface treatment process, the exposed surface of the semiconductorlayer 4 is treated and therefore formed into the ohmic contact layer 4a, as shown in FIG. 23. The surface treatment in this embodiment is aphosphorizing treatment using PH₃ gas, in which the RF power is about5-12 KW, the atmospheric pressure is about 100-400 mT, and the flow rateis about 1000-4000 sccm.

Then, the remaining phororesist is removed to complete the manufactureprocess of the TFT-LCD array substrate in this embodiment. As shown inFIG. 15 and FIG. 16, after this patterning process, the semiconductorlayer 4 is formed on the gate insulating layer 3 and positioned over thegate electrode 2, the blocking layer 5 is formed on the semiconductorlayer 4, the semiconductor layer 4 exposed on both sides of the blockinglayer 5 is formed into the ohmic contact layer 4 a, the first via hole 8a is provided on the pixel electrode 9 and near the gate electrode, andthe gate pad via hole (not shown) is formed in the gate pad region. Theremaining photoresist may be removed before the surface treatmentprocess is performed.

Finally, on the substrate with the pattern shown in FIG. 15, thesource/drain metal film with a thickness of about 2000-3000 Å isdeposited by using a magnetron sputtering method, a thermal evaporationmethod or other film formation method. The source/drain metal film maybe formed by a metal such as Cr, W, Ti, Ta, Mo, Al, Cu and the like oran alloy of the above metals. In addition, the source/drain metal filmmay have a multi-layer structure formed by any combination of the abovemetals. The data line 11, the common electrode line 12, the sourceelectrode 6 and the drain electrode 7 are formed by a patterning processusing a normal mask, as shown in FIG. 13 and FIG. 14. After thispatterning process, one end of the source electrode 6 is connected withthe data line 11, and the other end thereof is positioned on the ohmiccontact layer 4 a on one side of the blocking layer 5 and connected withthe semiconductor layer 4 through the ohmic contact layer 4 a. One endof the drain electrode 7 is connected with the pixel electrode 9 throughthe first via hole 8 a, and the other end thereof is positioned on theohmic contact layer 4 a on the other side of the blocking layer 5 andconnected with the semiconductor layer 4 through the ohmic contact layer4 a. The TFT channel region is formed between the source electrode 6 andthe drain electrode 7 and covered by the blocking layer 5. The commonelectrode line 12 is formed in the pixel region and constitutes thestorage capacitor with the pixel electrode 9. In addition, the commonelectrode line may not be formed.

According to this embodiment of the TFT-LCD array substrate, the pixelelectrode, the gate line and the gate electrode are formed by the firstpatterning process; the semiconductor layer, the blocking layer and thefirst via hole are formed by the second patterning process; and the dataline, the common electrode line, the source electrode and the drainelectrode are formed by the third patterning process. Since theover-etching process and the physical bombing in the conventionaltechnology are avoided in this embodiment, the TFT-LCD array substratehas the advantages similar to those in the first embodiment. Inaddition, since only three patterning processes are employed in thisembodiment, the manufacture cost can be reduced and the productionperiod can be shortened compared with the conventional technology withfour patterning processes. Therefore, the production efficiency can besignificantly improved.

Based on the above described embodiments, the TFT-LCD array substrate ofthe invention can be manufactured by increasing the number of thepatterning processes and selecting different materials or materialcombinations. For example, the patterns formed in the first patterningprocess according to the embodiment may be completed by two patterningprocesses, that is, the pixel electrode is formed by a patterningprocess with a normal mask, the gate electrode and the gate line areformed by another patterning process with another normal mask, and thedetails of the two patterning processes are omitted here for simplicity.

According to the invention, the embodiment of a method of manufacturinga TFT-LCD array substrate may comprise the following steps:

Step 1, sequentially depositing a transparent conductive film and a gatemetal film on a substrate, and forming a pixel electrode, a gate lineand a gate electrode by a patterning process;

Step 2, depositing a gate insulating layer and a semiconductor film andforming a semiconductor layer by performing patterning processes on thesubstrate after the Step 1, wherein two separate parts of the surface ofthe semiconductor layer is treated by a surface treatment process toform into an ohmic contact layer; and

Step 3, depositing a source/drain metal film on the substrate after theStep 2, and forming a data line, a source electrode and a drainelectrode by a patterning process, wherein the source electrode and thedrain electrode respectively are connected with the semiconductor layerthrough the ohmic contact layer.

In the method of the above embodiment, the surface treatment to thesemiconductor layer is a phosphorizing treatment using PH3 gas, in whichthe RF power is about 5-12 KW, the atmospheric pressure is about 100-400mT and the flow rate is about 1000-4000 sccm. In addition, the thicknessof the semiconductor layer is about 500-1500 Å, and preferably is about500-1000 Å.

The embodiment of the method of manufacturing the TFT-LCD arraysubstrate according to the invention will be described in detail throughthe following examples.

A first example of the method of manufacturing the TFT-LCD arraysubstrate may comprise the following steps.

Step 11, sequentially depositing the transparent conductive film and thegate metal film on the substrate, and forming the pixel electrode, thegate line and the gate electrode by a patterning process;

Step 12, sequentially depositing the gate insulating layer and asemiconductor film by a PECVD method;

Step 13, forming the semiconductor layer by a patterning process with anormal mask, wherein the semiconductor layer is positioned over the gateelectrode;

Step 14, depositing a passivation layer by a PECVD method;

Step 15, forming a first via hole, a second via hole and a third viahole by a patterning process with a normal mask, wherein the first viahole is provided on the pixel electrode and exposes the pixel electrodetherein, and the second via hole and the third via hole are provided onthe semiconductor layer;

Step 16, treating the surface of the semiconductor layer exposed in thesecond via hole and the third via hole so that the surface of thesemiconductor layer in the second via hole and the third via hole isformed into the ohmic contact layer;

Step 17, depositing the source/drain metal film by a magnetronsputtering method or a thermal evaporation method; and

Step 18, forming the data line, the source electrode and the drainelectrode by a patterning process with a normal mask, wherein one end ofthe source electrode is connected with the data line, and the other endthereof is connected with the semiconductor layer through the ohmiccontact layer in the third via hole; one end of the drain electrode isconnected with pixel electrode through the first via hole, and the otherend thereof is connected with the semiconductor layer through the ohmiccontact layer in the second via hole; and a TFT channel region is formedbetween the source electrode and the drain electrode.

Further, a common electrode line may be formed in the Step 18. Thecommon electrode line and the pixel electrode can constitute a storagecapacitor.

In this example, the TFT-LCD array substrate is manufactured by fourpatterning process, in which the pixel electrode, the gate line and thegate electrode are formed by the first patterning process; thesemiconductor layer is formed by the second patterning process; thefirst via hole, the second via hole and the third via hole are formed bythe third patterning process, and the surface of the semiconductor layerexposed in the second via hole and the third via hole is treated so thatthe surface of the semiconductor layer in the second via hole and thethird via hole is formed into the ohmic contact layer; the data line,the source electrode and the drain electrode are formed by the fourthpatterning process. The manufacture process of this example has beendescribed in detail with reference FIG. 3 to FIG. 12.

A second example of the method of manufacturing the TFT-LCD arraysubstrate may comprise the following step.

Step 21, sequentially depositing the transparent conductive film and thegate metal film on the substrate, and forming the pixel electrode, thegate line and the gate electrode by a patterning process;

Step 22, sequentially depositing the gate insulating layer, asemiconductor film and a blocking film by a PECVD method;

Step 23, applying a photoresist layer on the blocking film, exposing thephotoresist layer with a triple-tone mask to form aphotoresist-completely-removed region, a photoresist-completely-retainedregion, a first photoresist-partially-retained region and a secondphotoresist-partially-retained region, wherein thephotoresist-completely-removed region corresponds to the region of thefirst via hole to be formed, the photoresist-completely-retained regioncorresponds to the region of a blocking layer to be formed, the secondphotoresist-partially-retained region corresponds to the region of thesemiconductor layer to be formed, and the firstphotoresist-partially-retained region corresponds to the region otherthan the above regions, and wherein after performing a developingprocess, the thickness of the photoresist in thephotoresist-completely-retained region is not changed, the photoresistin the photoresist-completely-removed region is completely removed, thethickness of the photoresist in the first photoresist-partially-retainedregion and the second photoresist-partially-retained region isdecreased, and the thickness of the photoresist in the secondphotoresist-partially-retained region is larger than that in the firstphotoresist-partially-retained region;

Step 24, etching away the blocking film, the semiconductor film and thegate insulating layer in the photoresist-completely-removed region by afirst etching process to form the first via hole;

Step 25, completely removing the photoresist in the firstphotoresist-partially-retained region by a first ashing process toexpose the blocking film in this region, and retaining the photoresistin the second photoresist-partially-retained region and thephotoresist-completely-retained region;

Step 26, etching away the blocking film and the semiconductor film inthe first photoresist-partially-retained region by a second etchingprocess to form the semiconductor layer, wherein the semiconductor layeris positioned over the gate electrode;

Step 27, completely removing the photoresist in the secondphotoresist-partially-retained region by a second ashing process toexpose the blocking film in this region, and retaining the photoresistin the photoresist-completely-retained region;

Step 28, etching away the blocking film in the secondphotoresist-partially-retained region by a third etching process to formthe blocking layer, wherein the semiconductor layer is exposed on bothsides of the blocking layer;

Step 29, treating the exposed surface of the semiconductor layer so thatthe surface of the semiconductor layer exposed on both sides of theblocking layer is formed into an ohmic contact layer, and removing theremaining photoresist; and

Step 30, depositing the source/drain metal film by a magnetronsputtering method or a thermal evaporation method, and forming the dataline, the source electrode and the drain electrode by a patterningprocess with a normal mask, wherein one end of the source electrode isconnected with the data line, and the other end thereof is connectedwith the semiconductor layer through the ohmic contact layer on one sideof the blocking layer; one end of the drain electrode is connected withpixel electrode through the first via hole, and the other end thereof isconnected with the semiconductor layer through the ohmic contact layeron the other side of the blocking layer; and a TFT channel region isformed between the source electrode and the drain electrode.

Further, a common electrode line may be formed in the Step 30. Thecommon electrode line and the pixel electrode constitute a storagecapacitor.

In this example, the TFT-LCD array substrate is manufactured by threepatterning process, in which the pixel electrode, the gate line and thegate electrode are formed by the first patterning process; thesemiconductor layer, the blocking layer and the first via hole areformed by the second patterning process; and the data line, the sourceelectrode and the drain electrode are formed by the third patterningprocess. The manufacture process of this example has been described indetail with reference FIG. 15 to FIG. 23.

In the above examples, the surface treatment to the semiconductor layeris a phosphorizing treatment using PH₃ gas, in which the RF power isabout 5-12 KW, the atmospheric pressure is about 100-400 mT and the flowrate is about 1000-4000 sccm.

The above Step 1 (comprising the Step 11 or the Step 21) may beperformed as follows:

sequentially depositing the transparent conductive film and the gatemetal film on the substrate by a magnetron sputtering method or athermal evaporation method;

applying a photoresist layer on the gate metal film;

exposing the photoresist by a half-tone mask or a gray-tone mask to forma photoresist-completely-removed region, aphotoresist-completely-retained region and aphotoresist-partially-retained region, wherein thephotoresist-completely-retained region corresponds to the region of thegate line and the gate electrode, the photoresist-partially-retainedregion corresponds to the region of the pixel electrode, and thephotoresist-completely-removed region corresponds to the region otherthan the above regions, and wherein after performing a developingprocess, the thickness of the photoresist in thephotoresist-completely-retained region is not changed, the photoresistin the photoresist-completely-removed region is completely removed, andthe thickness of the photoresist in the photoresist-partially-retainedregion is decreased;

etching away the gate metal film and the transparent conductive film inthe photoresist-completely-removed region by a first etching process toform the gate electrode and the gate line;

completely removing the photoresist in thephotoresist-partially-retained region by an ashing process to expose thegate metal film in this region and retaining the photoresist in thephotoresist-completely-retained region;

etching away the gate metal film in the photoresist-partially-retainedregion by a second etching process to form the pixel electrode; and

removing the remaining photoresist.

In the above Step 1, the pixel electrode, the gate line and the gateelectrode are simultaneously formed in a same patterning process bymulti-step etching process. The manufacture process of the Step 1 hasbeen described in detail with reference FIG. 5 to FIG. 8.

By the method of manufacturing the TFT-LCD array substrate according tothe embodiments of the invention, the conventional over-etching processand the conventional physical bombing to the semiconductor layer can beavoided, and the multi-step etching process during forming theconventional TFT channel region can also be avoided, thus thesemiconductor layer can have a small thickness such as 500-1500 Å.Therefore, the turn-off current of the thin film transistor can besignificantly decreased, the period of holding the voltage of the pixelelectrode can be increased, the performance of the TFT-LCD arraysubstrate can be improved and the product yield can be increased. In thesecond embodiment employing three patterning processes, the cost can befurther reduced and the production period can be further shortedcompared to the conventional method employing four patterning processes.

It should be appreciated that the embodiments described above areintended to illustrate but not limit the present invention. Although thepresent invention has been described in detail herein with reference tothe preferred embodiments, it should be understood by those skilled inthe art that the present invention can be modified and some of thetechnical features can be equivalently substituted without departingfrom the spirit and scope of the present invention.

1. A thin film transistor liquid crystal display (TFT-LCD) arraysubstrate, comprising a gate line, a data line, a pixel electrode and athin film transistor, wherein the pixel electrode and the thin filmtransistor are formed in a pixel region defined by intersecting of thegate line and the data line, and the thin film transistor comprises agate electrode, a semiconductor layer, a source electrode and a drainelectrode, and wherein two separate parts of the surface of thesemiconductor layer are treated by a surface treatment to form into anohmic contact layer, and the source electrode and the drain electrodeare connected with the semiconductor layer through the ohmic contactlayer in the two separate parts, respectively.
 2. The TFT-LCD arraysubstrate according to claim 1, wherein the surface treatment to thesemiconductor layer comprises a phosphorizing treatment using PH₃ gas,in which the RF power is 5-12 KW, the atmospheric pressure is 100-400 mTand the flow rate is 1000-4000 sccm.
 3. The TFT-LCD array substrateaccording to claim 1, wherein a thickness of the semiconductor layer is500-1000 Å.
 4. The TFT-LCD array substrate according to claim 1, whereinthe pixel electrode made of a transparent conductive film is formed onthe substrate, and the transparent conductive film is also retainedbelow the gate electrode and the gate line.
 5. The TFT-LCD arraysubstrate according to claim 1, wherein a gate insulating layer isformed on the pixel electrode, the gate line and the gate electrode, thesemiconductor layer is formed on the gate insulating layer andpositioned over the gate electrode, a passivation layer is formed on thesemiconductor layer to cover the entirety of the substrate, a second viahole and a third via hole are provided in the passivation layer on thesemiconductor layer, the surface of the semiconductor layer exposed inthe second via hole and the third via hole is treated by the surfacetreatment to form into the ohmic contact layer, the source electrode andthe drain electrode are fowled on the passivation layer, the sourceelectrode is connected with the semiconductor layer through the ohmiccontact layer in the third via hole, and the drain electrode isconnected with the semiconductor layer through the ohmic layer in thesecond via hole.
 6. The TFT-LCD array substrate according to claim 5,wherein a first via hole is further provided in the passivation layer,the pixel electrode is exposed in the first via hole, and the drainelectrode is connected with the pixel electrode through the first viahole.
 7. The TFT-LCD array substrate according to claim 1, wherein agate insulating layer is formed on the pixel electrode, the gate lineand the gate electrode, the semiconductor layer is formed on the gateinsulating layer and positioned over the gate electrode, a blockinglayer is formed on a portion of the semiconductor layer, the separateparts of the surface of the semiconductor layer exposed on both sides ofthe blocking layer are treated by the surface treatment to form into theohmic contact layer, the source electrode is connected with thesemiconductor layer through the ohmic contact layer on one side of theblocking layer, and the drain electrode is connected with thesemiconductor layer through the ohmic layer on the other side of theblocking layer.
 8. The TFT-LCD array substrate according to claim 7,wherein a first via hole is provided in the gate insulating layer andthe drain electrode is connected with the pixel electrode through thefirst via hole.
 9. The TFT-LCD array substrate according to claim 8,wherein the gate insulating layer, the semiconductor layer, the blockinglayer and the first via hole are formed in a same patterning process.10. A method of manufacturing a thin film transistor liquid crystaldisplay (TFT-LCD) array substrate, comprising: Step 1 of sequentiallydepositing a transparent conductive film and a gate metal film on asubstrate, and patterning the transparent conductive film and the gatemetal film to form a pixel electrode, a gate line and a gate electrode;Step 2 of depositing a gate insulating layer and a semiconductor film onthe substrate after the Step 1 and patterning the semiconductor film toform a semiconductor layer, wherein two separate parts of the surface ofthe semiconductor layer is treated by a surface treatment process toform into an ohmic contact layer; and Step 3 of depositing asource/drain metal film on the substrate after the Step 2, andpatterning the source/drain metal film to form a data line, a sourceelectrode and a drain electrode by a patterning process, wherein thesource electrode and the drain electrode respectively are connected withthe semiconductor layer through the ohmic contact layer in the twoseparate parts.
 11. The method of claim 10, wherein the surfacetreatment to the semiconductor layer comprises a phosphorizing treatmentusing PH₃ gas, in which the RF power is 5-12 KW, the atmosphericpressure is 100-400 mT, and the flow rate is 1000-4000 sccm.
 12. Themethod of claim 10, wherein a thickness of the semiconductor layer is500-1000 Å.
 13. The method of claim 10, wherein the Step 1 comprises:applying a photoresist layer on the gate metal film after sequentiallydepositing the transparent conductive film and the gate metal film onthe substrate; exposing the photoresist by a half-tone mask or agray-tone mask to form a photoresist-completely-removed region, aphotoresist-completely-retained region and aphotoresist-partially-retained region, wherein thephotoresist-completely-retained region corresponds to the region of thegate line and the gate electrode, the photoresist-partially-retainedregion corresponds to the region of the pixel electrode, and thephotoresist-completely-removed region corresponds to the region otherthan the above regions, and wherein after performing a developingprocess, the thickness of the photoresist in thephotoresist-completely-retained region is not changed, the photoresistin the photoresist-completely-removed region is completely removed, andthe thickness of the photoresist in the photoresist-partially-retainedregion is decreased; etching away the gate metal film and thetransparent conductive film in the photoresist-completely-removed regionby a first etching process to form the gate electrode and the gate line;completely removing the photoresist in thephotoresist-partially-retained region by an ashing process to expose thegate metal film in this region and retaining the photoresist in thephotoresist-completely-retained region; etching away the gate metal filmin the photoresist-partially-retained region by a second etching processto form the pixel electrode; and removing the remaining photoresist. 14.The method of claim 10, wherein the Step 2 comprises: sequentiallydepositing the gate insulating layer and the semiconductor film on thesubstrate after the Step 1; forming the semiconductor layer by apatterning process with a normal mask, wherein the semiconductor layeris positioned over the gate electrode; depositing a passivation layer;forming a first via hole, a second via hole and a third via hole by apatterning process with a normal mask, wherein the first via hole isprovided on the pixel electrode and exposes the pixel electrode, thesecond via hole and the third via hole are provided on the semiconductorlayer; and treating the surface of the semiconductor layer exposed inthe second via hole and the third via hole by a surface treatment sothat the surface of the semiconductor layer exposed in the second viahole and the third via hole is formed into the ohmic contact layer. 15.The method of claim 14, wherein the Step 3 comprises: depositing thesource/drain metal film on the substrate after the Step 2; and formingthe data line, the source electrode and the drain electrode by apatterning process with a normal mask, wherein one end of the sourceelectrode is connected with the data line, and the other end thereof isconnected with the semiconductor layer through the ohmic contact layerin the third via hole; one end of the drain electrode is connected withpixel electrode through the first via hole, and the other end thereof isconnected with the semiconductor layer through the ohmic contact layerin the second via hole; and a TFT channel region is formed between thesource electrode and the drain electrode.
 16. The method of claim 10,wherein the Step 2 comprises: sequentially depositing the gateinsulating layer, the semiconductor film and a blocking film on thesubstrate after the Step 1; applying a photoresist layer on the blockingfilm; exposing the photoresist layer by a triple-tone mask to form aphotoresist-completely-removed region, a photoresist-completely-retainedregion, a first photoresist-partially-retained region and a secondphotoresist-partially-retained region, wherein thephotoresist-completely-removed region corresponds to the region of afirst via hole, the photoresist-completely-retained region correspondsto the region of a blocking layer, the secondphotoresist-partially-retained region corresponds to the region of thesemiconductor layer, and the first photoresist-partially-retained regioncorresponds to the region other than the above regions, and whereinafter performing a developing process, the thickness of the photoresistin the photoresist-completely-retained region is not changed, thephotoresist in the photoresist-completely-removed region is completelyremoved, the thickness of the photoresist in the firstphotoresist-partially-retained region and the secondphotoresist-partially-retained region is decreased, and the thickness ofthe photoresist in the second photoresist-partially-retained region islarger than that in the first photoresist-partially-retained region;etching away the blocking film, the semiconductor film and the gateinsulating layer in the photoresist-completely-removed region by a firstetching process to form the first via hole; completely removing thephotoresist in the first photoresist-partially-retained region by afirst ashing process to expose the blocking film in this region andretaining the photoresist in the second photoresist-partially-retainedregion and the photoresist-completely-retained region; etching away theblocking film and the semiconductor film in the firstphotoresist-partially-retained region by a second etching process toform the semiconductor layer, wherein the semiconductor layer ispositioned over the gate electrode; completely removing the photoresistin the second photoresist-partially-retained region by a second ashingprocess to expose the blocking film in this region, and retaining thephotoresist in the photoresist-completely-retained region; etching awaythe blocking film in the second photoresist-partially-retained region bya third etching process to form the blocking layer, wherein thesemiconductor layer is exposed on both sides of the blocking layer;treating the exposed surface of the semiconductor layer by the surfacetreatment so that the surface of the semiconductor layer exposed on bothsides of the blocking layer is formed into the ohmic contact layer, andremoving the remaining photoresist.
 17. The method of claim 16, whereinthe Step 3 comprises: depositing the source/drain metal film on thesubstrate after the Step 2, and forming the data line, the sourceelectrode and the drain electrode by a patterning process with a normalmask, wherein one end of the source electrode is connected with the dataline, and the other end thereof is connected with the semiconductorlayer through the ohmic contact layer on one side of the blocking layer;one end of the drain electrode is connected with pixel electrode throughthe first via hole, and the other end thereof is connected with thesemiconductor layer through the ohmic contact layer on the other side ofthe blocking layer; and a TFT channel region is formed between thesource electrode and the drain electrode.